Nonvolatile memory device and method of operating the same

ABSTRACT

A nonvolatile memory device comprises a memory cell array including a number of bit lines commonly coupled to a source line and each coupled to a number of memory cells, a delay unit configured to delay a sense signal in response to a voltage level of the source line and to output a delayed sense signal, and a page buffer unit configured to sense voltage levels of the bit lines in response to the delayed sense signal.

CROSS-REFERENCE TO RELATED APPLICATION

Priority to Korean patent application number 10-2009-0052259 filed onJun. 12, 2009, the entire disclosure of which is incorporated byreference herein, is claimed.

BACKGROUND

Exemplary embodiments relate to a nonvolatile memory device and a methodof operating the same and, more particularly, to a nonvolatile memorydevice and a method of operating the same, which are capable ofprohibiting malfunction of an operation for sensing the voltage level ofa bit line due to a source bouncing phenomenon.

In recent years, there has been an increasing demand for nonvolatilememory devices which can be electrically programmed and erased and whichdo not require the refresh function of rewriting data at specificintervals. To develop a high capacity of a memory device capable ofstoring a large amount of data, technology for the high degree ofintegration of memory cells is being developed.

To increase the degree of integration of memory cells, a NAND type flashmemory device in which a number of the memory cells are coupled inseries to form one cell string and two cell strings share one contacthas been developed. In such a NAND type flash memory device, program anderase operations are performed by controlling the threshold voltage of amemory cell while injecting or discharging electrons into or from afloating gate according to F-N tunneling.

Accordingly, an erased memory cell has a negative threshold voltagebecause electrons are discharged from a floating gate. A programmedmemory cell has a positive threshold voltage because electrons areinjected into a floating gate. However, the NAND type flash memorydevice has defects resulting from a charge gain or the loss of charges,and so several verification operations are performed on the memorydevice in relation to such characteristics. Here, a page buffer is usedto verify whether the program and erase operations have normally beenperformed.

The above-described flash memory device performs a program operation bycontrolling the voltage level of a bit line coupled to a memory cellusing the page buffer and performing a read operation or a programverification operation by sensing the voltage level of the bit line.

The known flash memory device includes a number of the memory cells andperforms the read or program verification operation on the memory cellscoupled to a number of the bit lines. Accordingly, some of the bit linesprecharged to a high voltage level have to be discharged to a lowvoltage level 0 V in response to program states. However, if currentflowing through a number of the bit lines is discharged to the sourceline, a source bouncing phenomenon is generated. Consequently, error canoccur during the read or program verification operation because the bitlines, that have to be discharged to a low voltage level, are not fullydischarged.

BRIEF SUMMARY

Exemplary embodiments relate to a nonvolatile memory device and a methodof operating the same, wherein a control signal to control theconnection between the bit line of a memory cell array and the sensenode of a page buffer unit is delayed in response to a bouncingpotential generated in the source line of the memory cell array.Accordingly, in the case where the voltage level of the bit line isdischarged in response to the state of a memory cell, the time forperforming a discharge operation can be increased, and so error during aread or program verification operation can be prohibited.

A nonvolatile memory device according to an aspect of the presentdisclosure includes a plurality of memory cells serially connectedbetween a plurality bit lines and a source line, a delay unit configuredto delay a sense signal in response to a voltage level of the sourceline and to output a delayed sense signal, and a page buffer unitconfigured to sense voltage levels of the bit lines in response to thedelayed sense signal.

The delay unit may delay the sense signal in proportion to the voltagelevel of the source line and outputs the delayed sense signal.

The page buffer unit may include a latch unit configured to temporarilystore program data or to sense and store verification data via a sensenode, a bit line sense unit coupled between the sense node and aselected bit line among the number of bit lines and configured totransfer the voltage level of the selected bit line to the sense node inresponse the delayed sense signal, and a precharge unit coupled to thesense node and configured to precharge the sense node in response to aprecharge signal to precharge the selected bit line coupled to the sensenode.

The bit line sense unit may precharge the selected bit line for acertain period of time and then senses the voltage level of the selectedbit line which varies in response to a program state of a selectedmemory cell of the memory cells.

The delay unit may include a control signal generator configured togenerate a number of control signals in response to the voltage level ofthe source line, a delay time control unit configured to control a rateof an increase in a pull-up voltage in response to a number of thecontrol signals, and a delayed signal generator configured to delay thesense signal and to generate the delayed sense signal, wherein thedelayed signal generator controls a time that the sense signal isdelayed in response to the rate of the increase in the pull-up voltage.

The control signal generator may include a number of comparators. Thecomparators compare the voltage level of the source line and a number ofrespective reference voltages with different voltage levels and output anumber of the respective control signals.

The delay time control unit may include a number of transistors coupledin parallel to a terminal for a power source voltage. The transistorscontrol the rate of the increase in the pull-up voltage in response to anumber of the respective control signals.

The delayed signal generator may include a number of inverter units.Each of the inverter units includes pull-up units. Here, the speed of apull-up operation is controlled in response to the pull-up voltagesupplied to the pull-up units, and so the time that each of the inverterunits is inverted is controlled by the controlled speed of the pull-upoperation.

According to another aspect of the present disclosure, there is provideda method of operating a nonvolatile memory device including a pagebuffer unit and a plurality of memory cells serially connected between aplurality bit lines and a source line, and the page buffer unit includesa bit line sense unit coupling a selected bit line and a sense node. Themethod includes coupling the selected bit line to the sense node,precharging the selected bit line by supplying a power source voltage tothe sense node, changing a voltage level of the selected bit line inresponse to a program state of a selected memory cell, when a voltagelevel of the source line rises, delaying a sense signal in proportion tothe voltage level of the source line, and sensing the voltage level ofthe selected bit line through the sense node in response to a delayedsense signal.

A timing at which the voltage level of the selected bit line is sensedand the time for changing the voltage level of the selected bit line arecontrolled in response to the delayed sense signal.

If the voltage level of the source line rises and so the time taken todischarge the voltage level of the selected bit line increases, a timingat which the voltage level of the selected bit line is sensed isdelayed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the configuration of a nonvolatile memory device accordingto an embodiment of this disclosure;

FIG. 2 is a diagram showing the connection relationship between a delayunit and the memory cell array of the nonvolatile memory deviceaccording to an embodiment of this disclosure;

FIG. 3 is a circuit diagram of the page buffer unit of the nonvolatilememory device according to an embodiment of this disclosure;

FIG. 4 is a detailed circuit diagram of the delay unit shown in FIG. 2;and

FIG. 5 is a waveform showing signals of the nonvolatile memory deviceand the voltage levels of a word line according to an embodiment of thisdisclosure.

DESCRIPTION OF EMBODIMENTS

Hereinafter, some embodiments of the present disclosure will bedescribed in detail with reference to the accompanying drawings. Thefigures are provided to allow those having ordinary skill in the art tounderstand the scope of the embodiments of the disclosure.

FIG. 1 shows the configuration of a nonvolatile memory device accordingto an embodiment of this disclosure.

Referring to FIG. 1, the nonvolatile memory device includes a memorycell array 110, a control signal generation unit 120, a delay unit 130,and a page buffer unit 140.

The memory cell array 110 includes a number of bit lines each having anumber of memory cells coupled in series thereto. A detailedconfiguration of the memory cell array 110 is described later.

When the nonvolatile memory device is operated, the control signalgeneration unit 120 is configured to generate a sense signal PBSENSE.

The delay unit 130 is configured to delay the sense signal PBSENSE for aspecific period of time corresponding to the voltage level V_SL of thesource line of the memory cell array 110 and to output a delayed sensesignal Del_PBSENSE.

The page buffer unit 140 is configured to couple a bit line of thememory cell array 110 with the sense node of the page buffer unit 140 inresponse to the delayed sense signal Del_PBSENSE and to sense theprogram state of a memory cell.

FIG. 2 is a diagram showing the connection relationship between thedelay unit 130 and the memory cell array 110 of the nonvolatile memorydevice according to an embodiment of this disclosure.

Referring to FIG. 2, the memory cell array 110 includes a plurality ofmemory cells serially connected between a plurality bit lines BL1 to BL5and a source line SL.

The delay unit 130 is configured to delay the sense signal PBSENSE for aspecific period of time corresponding to the voltage level V_SL of thesource line SL of the memory cell array 110 and to output the delayedsense signal Del_PBSENSE.

FIG. 3 is a circuit diagram of the page buffer unit 140 of thenonvolatile memory device according to an embodiment of this disclosure.

The page buffer unit 140 includes a number of page buffers. It is to benoted that in the embodiment of the present disclosure, only one pagebuffer is illustrated for the sake of convenience.

Referring to FIG. 3, the memory cell array 110 includes the memory cellsfor storing data, word lines WL<0> to WL<31> for selecting and enablingthe memory cells, and bit lines BLe and BLo for inputting and outputtingdata to and from the memory cells. The memory cell array 110 has astructure in which the plurality of word lines WL<0> to WL<31> and theplurality of bit lines BSLe and BSLo are arranged in a matrix form. Thememory cell array 110 has the memory cells coupled in series between asource select transistor SSL and a drain select transistor DSL, which iscalled a string structure. The gates of the memory cells are coupled tothe respective word lines. A set of the memory cells in common coupledto the same word line is called a page. A plurality of the stringscoupled to the respective bit lines is coupled in parallel to a commonsource line, thus constituting a memory block.

The page buffer unit 140 includes a bit line selection unit 141, a bitline sense unit 143, a sense node precharge unit 142, a data latch unit145, a data transfer unit 144, a data set unit 146, and a sense nodesense unit 147. The bit line selection unit 141 is configured toselectively couple a sense node SO via a bit line sense unit 143 with abit line coupled to a specific cell. The bit line sense unit 143 isconfigured to selectively couple the sense node SO with a bit linecoupled to a specific cell and to sense data stored in the specific cellduring read and program verification operations. The sense nodeprecharge unit 142 is configured to supply the sense node SO with a highpower source voltage. The data latch unit 145 is configured totemporarily store verification data read from a specific cell. The datatransfer unit 144 is configured to supply the sense node SO with datastored in the data latch unit 145 during a program operation. The dataset unit 146 is configured to input data to the data latch unit 145. Thesense node sense unit 147 is configured to supply a ground voltage to aspecific node of the data latch unit 145 in response to a voltage levelof the sense node SO.

The bit line selection unit 141 includes an NMOS transistor N13 and anNMOS transistor N14. The NMOS transistor N13 is configured to couple theeven bit line BLe with the sense node SO via the bit line sense unit 143in response to a first bit line selection signal BSLe. The NMOStransistor N14 is configured to couple the odd bit line BLo with thesense node SO via the bit line sense unit 143 in response to a secondbit line selection signal BSLo.

The bit line selection unit 141 further includes a control signal inputterminal, an NMOS transistor N11, and an NMOS transistor N12. Thecontrol signal input terminal is configured to supply a control signalVIRPWR having a specific voltage level. The NMOS transistor N11 isconfigured to couple the even bit line BLe with the control signal inputterminal in response to a first discharge signal DISCHe. The NMOStransistor N12 is configured to couple the odd bit line BLo with thecontrol signal input terminal in response to a second discharge signalDISCHo.

The bit line sense unit 143 is configured to selectively couple the bitline selection unit 141 and the sense node SO in response to a delayedsense signal Del_PBSENSE. To this end, the bit line sense unit 143includes an NMOS transistor N15 coupled between the bit line selectionunit 141 and the sense node SO. A detailed operation of the bit linesense unit 143 will be described hereinafter.

The sense node precharge unit 142 is configured to supply a power sourcevoltage VDD to the sense node SO in response to a precharge signalPRECH_b. To this end, the sense node precharge unit 142 includes a PMOStransistor P1 coupled between the sense node SO and a terminal for thepower source voltage VDD. A detailed operation of the sense nodeprecharge unit 142 will be described hereinafter.

The data latch unit 145 is configured to temporarily store data to beprogrammed into a specific cell or to temporarily store data read from aspecific cell. To this end, the data latch unit 145 includes a firstinverter IV1 and a second inverter IV2. Here, the output terminal of thefirst inverter IV1 is coupled to the input terminal of the secondinverter IV2, and the output terminal of the second inverter IV2 iscoupled to the input terminal of the first inverter IV1.

A node at which the output terminal of the first inverter IV1 is coupledto the input terminal of the second inverter IV2 is called a first nodeQb. A node at which the output terminal of the second inverter IV2 iscoupled to the input terminal of the first inverter IV1 is called asecond node Q.

For example, in the case where data of a high voltage level are suppliedto the first node Qb, the corresponding data are inverted by the secondinverter IV2, and so data of a low voltage level are supplied to thesecond node Q, and the data of a low voltage level are again inverted bythe first inverter IV1. Consequently, a data storage phenomenon occursin a manner that the data of a high voltage level supplied to the firstnode Qb remains intact. To the contrary, in the case in which data of alow voltage level are supplied to the first node Qb, the correspondingdata are inverted by the second inverter IV2, data of a high voltagelevel are supplied to the second node Q, the data of a high voltagelevel are again inverted by the first inverter IV1. Consequently, a datastorage phenomenon occurs in a manner that the data of a low voltagelevel supplied to the first node Qb remains intact.

The data transfer unit 144 is configured to selectively supply the sensenode SO with data stored in the first node Qb or the second node Q ofthe data latch unit 145. To this end, the data transfer unit 144includes a first transfer transistor N17 configured to selectivelycouple the first node Qb with the sense node SO and a second transfertransistor N16 configured to selectively couple the second node Q withthe sense node SO.

The first transfer transistor N17 transfers data, stored in the firstnode Qb, to the sense node SO in response to a first data transfersignal TRAN. Furthermore, the second transfer transistor N16 transfersdata, stored in the second node Q, to the sense node SO in response to asecond data transfer signal TRAN_N.

Accordingly, in the case where data stored in the first node Qb issought to be transferred to the sense node SO, the first data transfersignal TRAN of a high voltage level is supplied to the first transfertransistor N17. In the case where data stored in the second node Q issought to be transferred to the sense node SO, the second data transfersignal TRAN_N of a high voltage level is supplied to the second transfertransistor N16.

The data set unit 146 includes a first data set transistor N19 and asecond data set transistor N18. The first data set transistor N19 isconfigured to supply the ground voltage to the first node Qb of the datalatch unit 145. The second data set transistor N18 is configured tosupply the ground voltage to the second node Q of the data latch unit145.

The first data set transistor N19 is coupled between the sense nodesense unit 147 and the first node Qb and configured to supply the groundvoltage, received from the sense node sense unit 147, to the first nodeQb in response to a first data set signal RESET.

Furthermore, the second data set transistor N18 is coupled between thesense node sense unit 147 and the second node Q and configured to supplythe ground voltage, received from the sense node sense unit 147, to thesecond node Q in response to a second data set signal SET.

The sense node sense unit 147 is configured to supply the ground voltageto the data set unit 146 in response to a voltage level of the sensenode SO. To this end, the sense node sense unit 147 includes an NMOStransistor N20 coupled between the data set unit 146 and the groundterminal.

Accordingly, the ground voltage is supplied to the data set unit 146 inresponse to a voltage level of the sense node SO. Only when the voltagelevel of the sense node SO is in a high voltage level, the groundvoltage is supplied to the data set unit 146. Here, when the first dataset signal RESET of a high voltage level is supplied to the first dataset transistor N19, the ground voltage is supplied to the first node Qb.It is considered that data of a low voltage level have been supplied tothe first node Qb. However, when the second data set signal SET of ahigh voltage level is supplied to the second data set transistor N18,the ground voltage is supplied to the second node Q. It is consideredthat data of a high voltage level have been supplied to the first nodeQb.

FIG. 4 is a detailed circuit diagram of the delay unit 130 shown in FIG.2.

Referring to FIG. 4, the delay unit 130 includes a control signalgenerator 131, a delay time controller 132, and a delayed signalgenerator 133.

The control signal generator 131 includes a PMOS transistor PMOS1 and anumber of comparators 131_1 to 131_N. The PMOS transistor PMOS1 isconfigured to receive the voltage level V_SL of the source line SL inresponse to a compensation enable signal SL_Com which is enabled at alow voltage level when an evaluation operation for the bit lines coupledto the page buffer unit is started and to output the voltage level V_SLto the comparators 131_1 to 131_N. The comparators 131_1 to 131_N areconfigured to compare the voltage level V_SL of the source line SL and anumber of respective reference voltages Ref1 to RefN and to output anumber of respective control signals Con_1 to Con_N as results of thecomparison. For example, in the case where the voltage level V_SL of thesource line SL is less than each of the reference voltages Ref1 to RefNbecause a bouncing phenomenon has not occurred, the control signalsCon_1 to Con_N, each having a low voltage level, are outputted. With agradual increase in the voltage level V_SL of the source line SL, thenumber of control signals Con_1 to Con_N outputted at a high voltagelevel is increased.

The delay time controller 132 includes a number of PMOS transistorsPMOS_1 to PMOS_N. The PMOS transistors PMOS_1 to PMOS_N are coupled inparallel to the terminal for the power source voltage VDD and are turnedon in response to the respective control signals Con_1 to Con_N and tooutput a pull-up voltage UP_V. For example, with an increase in thenumber of control signals Con_1 to Con_N outputted at a high voltagelevel, the pull-up voltage UP_V rapidly rises.

The delayed signal generator 133 includes a first inverter unit 133A anda second inverter unit 133B. The first inverter unit 133A and the secondinverter unit 133B are coupled in series to each other, and anadditional inverter unit can be further included according to thedesign. The first inverter unit 133A and the second inverter unit 133Bhave a similar structure, and so only the first inverter unit 133A isdescribed as an example. The first inverter unit 133A includes a numberof PMOS transistors PMOS2 and PMOS3 and a number of NMOS transistorsNMOS1 and NMOS2. The PMOS transistors PMOS2 and PMOS3 are pull-up unitsto which the power source voltage VDD is supplied, and the NMOStransistors NMOS1 and NMOS2 are pull-down units whose output nodes aredischarged by the ground voltage VSS. The PMOS transistors PMOS2 andPMOS3 and the NMOS transistors NMOS1 and NMOS2 are turned on or off inresponse to the sense signal PBSENSE and are configured to output anoutput signal having an inverted logic level of a logic level of thesense signal PBSENSE through their output terminal. Here, the delay timeduring the inversion operation of the first inverter unit 133A ischanged in response to the rate of an increase of the pull-up voltageUP_V which is inputted to a node between the PMOS transistors PMOS2 andPMOS3. In other words, when the pull-up voltage UP_V is high, theinversion operation of the first inverter unit 133A is rapidlyperformed, and so the delay time is small. However, when the pull-upvoltage UP_V is low, the inversion operation of the first inverter unit133A is slowly performed, and so the delay time is increased.Consequently, a delay in the inversion operation of the first inverterunit 133A is determined in response to the pull-up operation of thefirst inverter unit 133A.

In the same manner that the delay time is changed during the inversionoperation of the first inverter unit 133A, the delay time is alsochanged during the inversion operation of the second inverter unit 133B.

As described above, the delay unit 130 is configured to increases thedelay time of the sense signal PBSENSE with a gradual increase in thevoltage level V_SL of the source line SL and to output the delayed sensesignal Del_PBSENSE.

FIG. 5 is a waveform showing signals of the nonvolatile memory deviceand the voltage levels of a word line according to an embodiment of thisdisclosure.

The operation of the nonvolatile memory device is described hereinafterwith reference to FIGS. 1 to 5.

First, the precharge signal PRECH_b that has been supplied at a highvoltage level is shifted to a low voltage level and then supplied to thePMOS transistor P1. Thus, the power source voltage VDD is supplied tothe sense node SO of the page buffer 140. At this time, the first bitline selection signal BSLe is supplied to the bit line selection unit141, and so the NMOS transistor N13 is turned on. Next, the delayedsense signal Del_PBSENSE of a high voltage level is supplied as avoltage level V1, thereby coupling the sense node SO with a selected bitline (e.g., the even bit line BLe). Accordingly, the even bit line BLeis precharged to a high voltage level (V1-Vth), wherein Vth is thethreshold voltage of the NMOS transistor N15.

After a lapse of a certain time, the delayed sense signal Del_PBSENSE ofa low voltage level is supplied, and so the connection between the evenbit line BLe and the sense node SO is broken. Consequently, a voltagelevel of the precharge signal PRECH_b shifts to a high voltage level,and then the power source voltage VDD is not supplied to the sense nodeSO.

The even bit line BLe is maintained at the high voltage level (V1-Vth)or discharged to have a low voltage level in response to the programstate of a memory cell selected from among a number of the memory cells.That is, the voltage level of the even bit line BLe is maintained ordischarged because the selected memory cell is turned on or off inresponse to a read or program verification voltage supplied to a wordline coupled to the selected memory cell. In other words, in the casewhere the selected memory cell has been programmed with a thresholdvoltage higher than a target threshold voltage, the even bit line BLe ismaintained at the high voltage level. Meanwhile, in the case where theselected memory cell has been programmed with a threshold voltage lessthan the target threshold voltage, the even bit line BLe is dischargedto have a low voltage level.

Here, if the voltage level of the even bit line BLe of a number of thebit lines is discharged, the amount of current flowing through thesource line SL sharply increases, resulting in a bouncing phenomenon inwhich the voltage level V_SL of the source line SL rises. Although thevoltage level of the even bit line BLe must be discharged as indicatedby a dotted line in FIG. 4, the amount of current discharged in the evenbit line BLe is decreased and the voltage level of the even bit line BLeis slowly discharged because a difference in the voltage level betweenthe even bit line BLe and the source line SL is decreased.

The delay unit 130 receives the sense signal PBSENSE from the controlsignal generator 120, delays the received sense signal PBSENSE for aspecific period of time corresponding to the voltage level V_SL of thesource line SL, and outputs the delayed sense signal Del_PBSENSE.

Table 1 shows the delay times of the delay unit 130 in response to thevoltage level V_SL of the source line SL.

TABLE 1 VOLTAGE LEVEL V_SL DELAY TIME OF OF SOURCE LINE DELAY UNIT  0 mV 0 nS  50 mV  5 nS 100 mV 10 nS 150 mV 15 nS 200 mV 20 nS

As shown in Table 1, the delay unit 130 delays the sense signal PBSENSEin proportion to the voltage level V_SL of the source line SL andoutputs the delayed sense signal Del_PBSENSE having a voltage level V2.

The delayed sense signal Del_PBSENSE is supplied to the bit line senseunit 143 of the page buffer unit 140, thereby coupling the sense node SOwith the even bit line BLe. Here, the time, that the even bit line BLeand the sense node SO are coupled together, is delayed by the delayedsense signal Del_PBSENSE. Even though the voltage level of the even bitline BLe is slowly discharged because of a source bouncing phenomenon,the discharge time is increased. Consequently, the even bit line BLecoupled to the sense node SO is sufficiently discharged to have a lowvoltage level, and a sense margin is increased when a sense operation isperformed using the page buffer unit 140. Accordingly, error during readand program verification operations can be prohibited.

According to the present disclosure, a control signal to control theconnection between a bit line of the memory cell array and the sensenode of the page buffer unit is delayed in response to a bouncingpotential generated in the source line of the memory cell array.Accordingly, in the case where the voltage level of the bit line isdischarged in response to the state of a memory cell, the time that ittakes to perform the discharge can be increased, and so error during aread or program verification operation can be prohibited.

1. A nonvolatile memory device, comprising: a plurality of memory cellscoupled between a plurality bit lines and a source line; a delay unitconfigured to delay a sense signal in response to a voltage level of thesource line and to output a delayed sense signal; and a page buffer unitconfigured to sense voltage levels of the bit lines in response to thedelayed sense signal.
 2. The nonvolatile memory device of claim 1,wherein the delay unit delays the sense signal in proportion to thevoltage level of the source line and outputs the delayed sense signal.3. The nonvolatile memory device of claim 1, wherein the page bufferunit comprises: a latch unit configured to temporarily store programdata or to sense and store verification data via a sense node; a bitline sense unit coupled between the sense node and a selected bit lineamong the plurality bit lines and configured to transfer the voltagelevel of the selected bit line to the sense node in response the delayedsense signal; and a precharge unit coupled to the sense node andconfigured to precharge the sense node in response to a precharge signalto precharge the selected bit line coupled to the sense node.
 4. Thenonvolatile memory device of claim 3, wherein the bit line sense unitprecharges the selected bit line for a certain period of time and thensenses the voltage level of the selected bit line which varies inresponse to a program state of a selected memory cell of the memorycells.
 5. A nonvolatile memory device of claim 1, wherein if the voltagelevel of the source line rises and a rate of discharge of the bit linesdecreases, a timing at which the voltage levels of the bit lines aresensed is delayed in response to the delayed sense signal so that a timefor discharging the voltage levels of the bit lines is increased.
 6. Thenonvolatile memory device of claim 5, wherein the delay unit delays thesense signal in proportion to the voltage level of the source line andoutputs the delayed sense signal.
 7. The nonvolatile memory device ofclaim 5, wherein the page buffer unit comprises: a latch unit configuredto temporarily store program data or to sense and store verificationdata via a sense node; a bit line sense unit coupled between the sensenode and a selected bit line among the bit lines and configured totransfer the voltage level of the selected bit line to the sense node inresponse the delayed sense signal; and a precharge unit coupled to thesense node and configured to precharge the sense node in response to aprecharge signal to precharge the selected bit line coupled to the sensenode.
 8. The nonvolatile memory device of claim 7, wherein the bit linesense unit precharges the selected bit line for a certain period of timeand then senses the voltage level of the selected bit line which variesin response to a program state of a selected memory cell of the memorycells.
 9. The nonvolatile memory device of claim 5, wherein the delayunit comprises: a control signal generator configured to generate anumber of control signals in response to the voltage level of the sourceline; a delay time control unit configured to control a rate of anincrease in a pull-up voltage in response to a number of the controlsignals; and a delayed signal generator configured to delay the sensesignal and to generate the delayed sense signal, wherein the delayedsignal generator controls a time that the sense signal is delayed inresponse to the rate of the increase in the pull-up voltage.
 10. Thenonvolatile memory device of claim 9, wherein: the control signalgenerator comprises a number of comparators, and the comparators comparethe voltage level of the source line and a number of respectivereference voltages with different voltage levels and output a number ofthe respective control signals.
 11. The nonvolatile memory device ofclaim 9, wherein: the delay time control unit comprises a number oftransistors coupled in parallel to a terminal for a power sourcevoltage, and a number of the transistors control the rate of theincrease in the pull-up voltage in response to a number of therespective control signals.
 12. The nonvolatile memory device of claim9, wherein: the delayed signal generator comprises a number of inverterunits, and each of the inverter units comprises pull-up units, wherein aspeed of a pull-up operation is controlled in response to the pull-upvoltage supplied to the pull-up units, and a time that each of theinverter units is inverted is controlled by the controlled speed of thepull-up operation.
 13. A method of operating a nonvolatile memory devicecomprising a page buffer unit and a plurality of memory cells coupledbetween a plurality bit lines and to a source line, and the page bufferunit comprises a bit line sense unit coupling a selected bit line and asense node, the method comprising: coupling the selected bit line to thesense node; precharging the selected bit line by supplying a powersource voltage to the sense node; changing a voltage level of theselected bit line in response to a program state of a selected memorycell; when a voltage level of the source line rises, delaying a sensesignal in proportion to the voltage level of the source line; andsensing the voltage level of the selected bit line through the sensenode in response to a delayed sense signal.
 14. The method of claim 13,wherein a timing at which the voltage level of the selected bit line issensed and a time for changing the voltage level of the selected bitline are controlled in response to the delayed sense signal.
 15. Themethod of claim 13, wherein if the voltage level of the source linerises and a time for discharging the voltage level of the selected bitline increases, a timing at which the voltage level of the selected bitline is sensed is delayed.